RTL Code Analysis and Verification Solution ALINT-PRO
Static design analysis tool that works on Windows/Linux.
"ALINT-PRO" is a verification solution that analyzes RTL code written in VHDL, Verilog, and SystemVerilog, focusing on coding styles and naming conventions, mismatches between RTL and synthesis results, smooth and optimal synthesis, correct FSM descriptions, issues in the later stages of design, problems with clock and reset trees, CDC, RDC, DFT, and coding for portability and reuse. This solution performs static analysis based on RTL and SDC (Synopsys Design Constraints) source files, identifying critical design issues early in the design phase and significantly contributing to the reduction of design time. By running ALINT-PRO before RTL simulation and logic synthesis, you can prevent design issues from propagating to downstream processes in the design flow, thereby reducing the number of revisions needed before design completion. *For more details, please refer to the PDF materials or feel free to contact us.*
- Company：アルデック・ジャパン
- Price：Other
